MICROELECTRONICS

Author: CASTRO LÓPEZ RAFAEL.
Year: 2004.
University: SEVILLA [www.us.es].
Place of defense: FACULTAD DE BIOLOGIA.
Place of preparation: FACULTAD DE FÍSICA, INSTITUTO DE MICROELECTRÓNICA DE SEVILLA.

Summary: Despite the spectacular progress made by the semiconductor industry, the ability to design integrated circuits under increasingly complex demands of time-to-market increasingly aggressive, it is not moving at the same pace that makes the integration capability. To reduce this gap (known as design gap) is currently one of the most interesting challenges facing the semiconductor industry. In this regard, the design of integrated circuits based on the concept of reusability (design reuse), is seen as one of the most efficient solutions that address this challenge. Unfortunately, and although this concept has been successfully developed in the digital environment, it is not yet ripe for implementation in the design of analog circuits and mixed-signal, an area where it improved productivity is even even more critical. This thesis comes in this context, with the aim of the study, development and validation of an efficient framework for the design based on reusability oriented analog circuits and mixed-signal. This framework has been based on three pillars: 1-A hierarchical design flow supported by appropriate CAD tools that enable the inclusion of reusable blocks, thereby significantly reducing the total design time. 2-A concept systematic and structured block reusable analog or mixed-signal. 3-A set of methods, tools and guidelines for design reusability (using the concepts of parameterization and capture design expertise) with whom we can develop these reusable blocks.

Author: García García Héctor.
Year: 2005.
University: VALLADOLID [www.uva.es].
Place of defense: E.T.S.I. Telecomunicación.
Place of preparation: E.T.S.I. Telecomunicación.

Summary: For more than 30 years there is a trend towards miniaturization of electronic devices, which are known as Moore's Law. However, they are reaching sizes of devices so small that there seems to be a physical limit that prevents enforcement of this law is not very long term. One problem is that the thickness of insulation used to insulate the gate MOSFET transistors is so thin that occur too many losses because of the tunnel effect. One solution is the replacement of insulation used, SiO2, by a higher dielectric constant. The objective of this thesis was the study of various insulating materials for use as new insulation door. These materials have been nitrides of silicon, aluminum oxide, hafnium oxide, titanium oxides, silicates of hafnium and other mixtures and compounds nanolaminados. To grow these materials, various techniques have been used for growth: ALD, HPRS and ECR-CVD. The properties were studied from technical characterization of electrical and non electrical appliances.

Author: SAMPEDRO MATARÍN CARLOS.
Year: 2006.
University: GRANADA [www.ugr.es].
Place of defense: FACULTAD DE CIENCIAS.
Place of preparation: FACULTAD DE CIENCIAS.

Summary: The present work has been carried out a study of the transport of electrons in transistors modulation speed (VMT) constructed from silicon devices double door on insulator (DGSOI) using approximations difusión-deriva and method Ensemble Monte Carlo (EMC) which is included correction of quantum physics. The transistor modulation speed (VMT) was nominated by Prof.. Sakaki of the University of Tokyo in 1982 as a means to achieve a rapid modulation of the flow ranging mobility of carriers instead of the same density as opposed to conventional MOSFETs. The concept was introduced originally introduced VMT thinking of semiconductor compounds III-V (heterostructures AlGaAs-GaAs). However, the recent development of the SOI technology, and in particular devices double door, has enabled the adaptation of the concept of variable speed technology to silicon on insulator. The technique used for this study was the numerical simulation of the electronic transport through the Monte Carlo method. It has been widely employed in the research group to study other structures such as Si-SiO2 present in conventional MOS transistors, silicon transistors stressed or SiGe transistors on single and double door silicon on insulator (SG-SOI and DGSOI). The dual-gate SOI devices have been in recent years a focus of inquiry because, basically, that have been proposed by the Roadmap for Industry Semiconductora, and the Workprogramme on IST in the European Union to expand capacity integrative conventional silicon technology beyond the barrier of 10nm. For the implementation of a transistor VMT with SOI technology, it is considered a transistor DGSOI with a thickness of silicon such that the device possesses two channels, A and B, with a different mobility. The difference in mobility between the two channels can be achieved, for example, intentionally degraded one of the two interfaces Si/SiO2. The modulation of the flow in the device is achieved by switching the load on the structure of the channel increased mobility of the lower mobility and vice versa. However, many issues still remain open these devices. To cite a few of them, it would be very interesting to know the time of commutation or whether the mechanisms used to intentionally degrade one of the channels, and how they affect the other channel. The work plan can be summarized as follows: Firstly been resolved so autoconsistente equations Poisson and Continuity approximate difusión-deriva bidimensional obtained a good agreement with the results obtained using conventional simulation tools such as PISCES II. Secondly, using as a stationary initial solution obtained in the previous step, studies have been conducted from time switching devices using the method VMT EMC comparing the results with those obtained for devices DGSOI and SGSOI of the same operating characteristics as conventional transistors . We also have studied the effects on the functioning of a VMT has the variation of certain parameters such as the thickness of the layer of silicon that forms the channel or the degradation mechanisms considered for the channel with low mobility. Finally, due to strong containment faced by carriers in devices foil ultradelgada (UTB) has also been studied the problem of transport in these devices in the light of quantum corrections first or 8 rden bas 5cd adas in the model gradient density . The investigation was initiated within the European project EXTRA coordinated by Professor Ahopelto center VTT in Finland and now comes within the network of Excellence EU IST-1-506844-NOE-SINANO. The results show that switching occurs in a more rapid in the VMT in the conventional MOSFET being further dependence on it less strong with the length of the channel. Such devices are expected to be able to operate in the so-called 'Teraherz Gap' for frequencies between a few hundred and a few GHz THz where conventional CMOS technology can not operate effectively. The main niche application is expected to be the security systems and medical instrumentation.